Fabless Semi. Companies 41m ago: Synopsys+OpenAI agentic AI for IC design workflows. RibbonFET + PowerVia memory IP for backside power delivery. CXL thousands-of-cores chips for near-memory compute. Huawei-DeepSeek co-designing AI silicon with MLA, sparse MoE, TileLang on domestic nodes. ASML supply constraints 2027-2028. Tata Dholera targeting 28-110nm mature nodes for analog/power/MCUs.
"Breaking the AI Infrastructure Power Wall": From Grid-to-xPU - AI infrastructure is scaling rapidly, driving higher rack power, compute density, and xPU power demands. These trends are exposing the limits of traditional power architectures and creating a new AI infrastructure "power wall." Navitas 2.0 marks a strategic shift toward high-power, high-growth markets,...
The Memory Wall and the Edge - The Memory Wall and the Edge By Dr. Jonathan Tapson, Chief Development Officer How Sequora Rethinks AI Acceleration Around Data Movement A funny thing happened in 2018, and the hardware industry has been reacting to it ever since. Memory stocks soared. NVIDIA became the most valuable company in The post...
[Blog] EU CRA Readiness: Five Priorities for Lifecycle Security - The European Union (EU) Cyber Resilience Act (CRA) has entered a critical phase. Vulnerability reporting requirements took effect Sept. 11, 2026, and broader compliance requirements apply beginning Dec. 11, 2027. In a recent Security Seminar, Lattice and OmniTrust discussed why readiness must become an...